Audio delay system

ABSTRACT

Variably delaying an audio signal by storing digital representions of the audio signal at sequential memory locations prescribed by an encoding pointer operating at one clock rate, and reading from the memory at sequential locations prescribed by a decoding pointer operating at the same or a different clock rate, with the difference in clock rates between the pointers prescribing the rate of change of delay. A memory addressing system in which a processor specifies the high-order portion of a memory address and a separate counter, clocked at a much higher rate than the processor, provides the low-order portion of the address.

A microfiche appendix is included in the application, consisting ofthree sheets, 114 pages.

BACKGROUND OF THE INVENTION

This invention relates to audio delay systems.

Such systems are used in the music industry to produce various soundeffects. An example of such a sound effect is the so-called "flange", inwhich an undelayed audio signal is mixed with a delayed audio signal,and the amount of delay is varied over time. When the two signals aremixed, they constructively interfere with each other at some frequenciesto create reinforcements, while destructively interfering with eachother at other frequencies to create cancellations. As the delay varies,the reinforcement and cancellation frequencies vary, producing theflange effect.

Typically, the delay is varied by varying the frequency of the clockcontrolling the rate at which the incoming analog audio signal isdigitally encoded, and the rate at which the digitally encoded signal isdecoded. For example, to obtain a four-to-one flange, the clock isvaried over a four-to-one range. The four-to-one variation in clockfrequency varies the time during which the encoded signal is resident inmemory, and thus the delay, by the same four-to-one ratio. Because clockfrequency variations can typically not be as wide as desired delayvariations (because sound fidelity will deteriorate as the result ofincreased quantization noise), it has typically been necessary to switchinto use a variable number of sequentially-arranged memory elements,each of which delays the encoded signal for a predetermined period oftime. Switching memory elements into use in this manner creates audibleencoding artifacts during the interval required to fill new memoryelements with encoded data.

SUMMARY OF THE INVENTION

In general the invention features, in a first aspect, providing variabledelay of an audio signal by storing digital representions of the audiosignal at sequential memory locations prescribed by an encoding pointeroperating at one clock rate, and reading from the memory at sequentiallocations prescribed by a decoding pointer operating at the same or adifferent clock rate, with the difference in clock rates between theencoding and decoding pointers prescribing the rate of change of delay.The pointers automatically wrap around from the highest address in thememory to the lowest, to make the memory appear functionally as a ringof memory locations. In preferred embodiments, adaptive delta modulationis used to encode and decode the audio signal; a microprocessorprescribes delay by prescribing a time schedule of changes in thedifference in clock rates between the encoding and decoding pointers;different flange effects are provided by storing appropriate schedulesof prescribed difference in encoding and decoding clock rates; variationof the addresses between which the decoding pointer skips providesoperator adjustment of the beginning and end points of repetitivelyplayed back short intervals of music. The invention has the advantage ofallowing instantaneous wide variations in delay (e.g., hundred to one)without any degradation in fidelity and without the production of anyaudible artifacts.

In a second aspect, the invention features a memory addressing system inwhich a processor specifies the high-order portion of a memory addressand a separate counter, clocked at a much higher rate than theprocessor, provides the low-order portion of the address. An overflowindication is provided the processor when the counter overflows. Inpreferred embodiments, there is provided an address register for storingthe current high-order address portion, a buffer register for storingthe next value of the high-order address portion, and means for loadingthe contents of the buffer register into the address register uponassertion of the overflow indication, and means for loading the bufferregister with a new high-order address portion in less than the timeinterval between successive overflow indications. The invention allows aslow (and thus less expensive) processor to address memory at a higherclock rate than it can itself operate.

In a third aspect, the invention features an audio delay system in whichseparate encoding and decoding clock signals are generated using anoscillator that provides a high-frequency clock signal, a divider thatdivides down the high-frequency clock signal to form one of the encodingand decoding clock signals, a pulse adding/removing circuit for addingor removing pulses to or from the high-frequency clock signal, toincrease or decrease its frequency, and a second divider for dividingthe output of the pulse adding/removing circuit to provide the other ofthe encoding and decoding clock signals. The invention has the advantageof being capable of providing clock signals separated only slightly infrequency without danger of the clocks locking in synchrony.

DESCRIPTION OF PREFERRED EMBODIMENTS Drawings

FIG. 1 is a block diagram of a preferred embodiment of the invention.

FIG. 2 is a plot illustrating a parabolic flange generated by saidembodiment.

FIG. 3 is a diagrammatic representation of the delay memory of saidpreferred embodiment.

FIG. 4 is a block diagram of another preferred embodiment of saidinvention.

FIG. 5 is a block diagram of the difference and summing circuitry andthe integrator shown in FIG. 1.

FIG. 6 is a schematic of the preferred implementation of the blockdiagram of FIG. 5.

Circuitry

Referring to FIG. 1, adaptive delta encoder 14 encodes analog inputsignal AIN to produce digital signal DIN, which is written into delaymemory 16 (a 64K byte RAM) at the 16-bit address specified by theencoding pointer EPOINT. Analog output signal AOUT is generated byadaptive delta decoder 18, using digital output signal DOUT, which isread from memory 16 at the 16-bit address specified by the decodingpointer DPOINT. Multiplexer 20 alternately connects DPOINT and EPOINT tothe address input of memory 16.

Analog output signal AOUT may be summed with input signal AIN (bycircuitry not shown) to produce a flange effect, or it may be useddirectly.

The encoding pointer EPOINT consists of four low order bits supplied by4-bit hardware counter 22 and twelve high order bits supplied by 12-bitencoder address register 24. Counter 22 is incremented approximatelyevery 33 microseconds by encoding clock ECLK, supplied by encoding clockcircuit 26, consisting of a simple 300 KHz oscillator circuit. Addressregister 24 is updated every sixteen clock intervals (roughly 500microseconds) by microprocessor 26 (a conventional 6803 microprocessor)via buffer register 28. When counter 22 overflows, it sends a carrysignal EC to address register 24 and microprocessor 26, therebyinstructing the address register to load the contents of buffer register28, which the microprocessor has supplied with the next 12-bit address(ordinarily one bit higher than the last address). The microprocessorhas roughly 500 microseconds following receipt of the counter overflowsignal EC to supply the buffer register 28 with the next 12-bit address.Providing such a lengthy period makes it possible to use a slow (andinexpensive) microprocessor. The two high order bits of counter 22 arereturned to the microprocessor as signal EP2.

Decoding pointer DPOINT is generated in a manner similar to that used togenerate the encoding pointer. The low-order four bits of DPOINT aresupplied by decoder counter 30; the twelve high order bits, by addressregister 32. Counter 30 is incremented by decoding clock DCLK, which isgenerated by voltage-to-frequency converter 36 (see below). Addressregister 32 is updated by microprocessor 26 via buffer register 34.Overflow line DC from counter 30 is used to instruct address register 32to load the contents of buffer register 34, and to inform microprocessor26 that it must reload the buffer register. The two high order bits ofcounter 30 are returned to the microprocessor as signal DP2.

The frequency of decoding clock DCLK is set by voltage to frequencyconverter 36, which is driven by the output of integrator 38. The inputto the integrator is the sum of signal A, the output of D/A converter40, and signal B, the output of difference circuit 42. Microprocessor 26drives the D/A converter, and thus directly establishes the level ofsignal A. Signal B is a voltage proportional to the difference infrequency of the encoding and decoding clocks; it is generated bydifference circuit 42 working in conjunction with pulse generators 44,46.

Operation

Operation of the preferred embodiment can be understood by examiningFIG. 3, in which memory 16 is shown as a ring of memory locations. Datais written into memory at the address specified by encoding pointerEPOINT, which travels fully around the 64K bits of the memoryapproximately every 1.7 seconds. Data is read from the memory at theaddress specified by decoding pointer DPOINT, which trails behind EPOINTby the amount of delay. The speed of the encoding pointer is set byfixed encoding clock ECLK, and is constant (except for drift in theoscillator frequency). Changes in delay are brought about by slightlyvarying (by a few percent) the decoding clock DCLK relative to theencoding clock ECLK, under control of the microprocessor. For example, aslight slowing down of DCLK will lengthen the delay by causing DPOINT tofall further behind EPOINT.

The microprocessor prescribes the variation between the encoding anddecoding clocks using the CLKDIFF signal supplied to A/D converter 40.The CLKDIFF signal prescribes the difference in frequency between theDCLK and ECLK, i.e., the rate of change of the difference in positionbetween the encoding and decoding pointers (as opposed to the actualposition of the pointers). During an initialization routine, themicroprocessor varies CLKDIFF to find the value that produces theminimum difference between DCLK and ECLK; that value is stored as thezero reference. The CLKDIFF signal is kept at the zero referencewhenever the amount of delay is to remain unchanged. A change in delayis brought about by varying CLKDIFF from the zero reference for someinterval. The use of an initializing routine to find a zero referenceallows the use of imprecise (and thus less expensive) circuits for theD/A converter 40, integrator 38, pulse generator circuits 44, 46, anddifference circuit 42. For example, the integrator may have an offsetbuilt into its output. Also, the oscillator circuit forming the encodingclock 26 may drift over time as much as 5 to 10% without ill effect. Thepulse generator circuits may generate pulses of different widths, solong as the difference remains constant with time and temperature.

A more exact description of the difference circuit 42, summing node 48,integrator 38, pulse generator circuits 44, and voltage-to-frequencyconverter 36 is given in FIGS. 5 and 6. The difference circuit andsumming node are implemented at the input to the same operationalamplifier 90 that provides the integration. A comparator 92 andsurrounding circuit provides the voltage-to-frequency converter.Referring to FIG. 6, pulse generator circuits 44 are implemented asone-shot pulse generating circuits 80, 82 (implemented as halves of asingle dual integrated circuit, each with precision external resistorand capacitor) and filters provided by capacitors 84, 86. The pulsetrains generated by the one-shot circuits are filtered to provide ananalog voltage representative of the frequency of ECLK and DCLK. Theoutput of D/A converter 40 (more precisely the output of the resistorladder of the converter) is presented at point A. To minimize noiseeffects, it is important that all ground connections 88 be separatelybrought to a common ground node (without intermediate trees orbranches).

To create a flange effect, such as the parabolic flange shown in FIG. 2(in which delay varies from about 3.0 milliseconds to a minimum of about100 microseconds, and back to 3.0 milliseconds, roughly every threeseconds), the CLKDIFF signal is varied over time according to apredetermined schedule. CLKDIFF is a maximum at the beginning and end ofeach cycle, at which times the slope of the delay curve in FIG. 2 is amaximum; CLKDIFF is a minimum at the middle of each cycle when the slopeof the delay curve is at a minimum.

Because the shape of the delay curve is produced in an open loopmanner--i.e., by specifying a schedule of changes in decoding clockfrequency over time--the actual delay curve generated tends to varysomewhat randomly from that shown in FIG. 2. In particular the downwardand upward halves of the parabolic curve in FIG. 2 may in practice notbe perfectly symmetrical. For example, the curve may end up with theshape shown in dashed lines. The microprocessor has a routine fordetecting the variation in the turning point of the flange (the closestapproach to zero delay) from the desired turning point, and for varyingthe starting point to minimize the variation. In the example shown, themicroprocessor would, after detecting that the actual delay variationwas as shown in dashed lines, reduce the starting delay by about 200microseconds to bring the turning point closer to the desired 100microseconds from the roughly 300 microseconds achieved in the priorcycle. The result of this adjustment from cycle to cycle is a pleasantsounding randomness in the degree of flanging.

The schedule for varying CLKDIFF is determined by the microprocessorusing the measured zero reference and the desired degree of delayvariation (set at the control panel). An iterative procedure is followedin which changes to CLKDIFF are made over time, the resulting change indelay is calculated (assuming an ideal D/A converter and integrator),and the schedule of changes to CLKDIFF is altered until the desireddelay changes are achieved.

During a flange cycle, the microprocessor monitors the delay between thetwo pointers EPOINT and DPOINT to assure that the delay never becomes sosmall as to allow the pointers to crossover, i.e., for the decodingpointer DPOINT to get ahead of the encoding pointer. If such an eventtook place, the decoded signal would instantaneously go from zero delayto approximately 1.7 seconds delay, something generally undesirablebecause of the musical discontinuity produced. For monitoring theseparation between the two pointers, the microprocessor has available toit all but the lowest order two bits of the pointer addresses. If themicroprocessor determines that a crossover is about to occur, itimmediately alters the CLKDIFF signal sufficiently to slow down thedecoding pointer and prevent crossover.

Variation in CLKDIFF brings about a change in the decoding clock DCLK bymeans of a feedback circuit. When CLKDIFF changes, output A of D/Aconverter 40 changes, thereby changing the input to integrator 38. Theoutput of integrator 38 then begins to change, bringing about a changein DCLK, thereby, in turn, changing output B of difference circuit 42.Eventually, if no further change is made to CLKDIFF, a new equilibriumpoint will be reached in which DCLK is changed sufficiently to exactlybalance the change in CLKDIFF, at which time the input to the integratorwill have returned to zero.

This feedback arrangement prevents the encoding and decoding clocks from"locking up" with one another even when they are operating at onlyslightly different frequencies. Without the feedback--e.g., if thedecoding clock was set directly by the CLKDIFF signal from themicroprocessor--noise generated at the instant that one clock changedstate would tend to cause the other clock to change state ahead of itsprescribed time, thereby locking the two clocks in synchrony. Thefeedback circuit prevents this from happening, because if such a lock upbegins the input to integrator 38 will remain constant, thereby causingthe integrator output to grow until the clocks are forced out ofsynchrony.

The preferred embodiment may also be used to produce what are known inthe music industry as "repeats". In this mode of operation, a panelswitch (e.g., a button) is used by the operator to initiate storage of1.7 seconds of music. The microprocessor saves the 0.2 seconds of musicpreceding depression of the panel switch and the following 1.5 seconds.After this 1.7 seconds of music has been stored in the memory, thedecoding pointer DPOINT can be made to move around the memory in avariety of ways to allow any portion of the recorded 1.7 second intervalto be repeated. For example, using panel controls the operator may movethe starting point of the repeated sequence to the 0.1 second mark(i.e., 0.1 seconds before he depressed the panel switch) and the endingpoint to the 1.5 second mark. To accomplish this, the microprocessorcauses the decoding pointer to skip from the address corresponding to1.5 seconds immediately to the address corresponding to 0.1 seconds,leaving out the intervening 0.3 seconds of music.

Typically, the operator will set either the beginning or end of theinterval to capture a desired sound, and then vary the other boundaryuntil a point is found at which the wrap-around transition (in theexample, the jump from the 1.5 second point ot the 0.1 second point)produces an acceptably minimal "click" in the sound. The invention worksparticularly well in this application because it allows the operator tovary the starting and stopping points of the repeated sound withoutintroducing any sound artifacts (e.g., "clicks") other than the oneinherent in the wrap-around transition itself.

In applications in which the delay is not varied, the encoding clockECLK may be switched into use for both the encoding and decodingpointers.

As the amount of delay is controlled by a microprocessor, it is possibleto program a sequence of different delay effects (e.g., a parabolicflange, followed by an echo (i.e., a constant delay), followed by a lesspronounced parabolic flange, and so on). Front panel controls (notshown) may be provided for such programming. Because the amount of delaycan be instantaneously varied from nearly zero to 1.7 seconds, it ispossible to switch between effects without introducing "clicks" or otherartifacts (other than those produced solely by the prescribed changes indelay).

Another embodiment of the invention is shown in FIG. 4. This embodimentdiffers from the embodiment shown in FIG. 1 in the manner in which theencoding and decoding clocks ECLK, DCLK are generated. Instead of thesimple 300 KHz oscillator for ECLK and feedback circuit for DCLK, thereis a single high frequency clock 100 (30 MHz crystal oscillator) onwhich both ECLK and DCLK are based. ECLK is generated by dividing the 30MHz clock using 100:1 divider 102, the output of which is the desired300 KHz encoding clock ECLK. The decoding clock is generated using anidentical 100:1 divider 104, but prior to entering the divider, theclock signal passes through a circuit 106 adapted to add or removepulses from the 30 MHz pulse stream. The frequency of added or removedpulses is proportional to CLKDIFF, set by the microprocessor. Forexample, to slow DCLK by 0.1% from ECLK, it is necessary to remove 0.1%of the pulses in the 30 MHz pulse stream, i.e., every thousandth pulse.This clock circuit is not susceptible to locking up, but does require asomewhat more expensive oscillator than the circuit of FIG. 1, as wellas the addition of the divider circuits and pulse adding/removingcircuit.

A set of schematics and a listing of microprocessor software for thepreferred embodiment of FIG. 1 are provided in the appendix. The listedsoftware is stored in two 2782 EPROMs shown in the schematics. The firstcolumn in the software listing is the address; the second is the datastored at that address; the third is the symbol name; the fourth is theinstruction mnemonic.

Other embodiments of the invention are within the scope of the followingclaims.

What is claimed is:
 1. A system for variably delaying an audio signal,said apparatus comprisingmemory means for storing a sequence of numberscomprising digital representions of consecutive portions of said audiosignal, addressing means for generating encoding and decoding pointersfor accessing said memory means, memory writing means for writing saidnumbers at sequential memory locations prescribed by said encodingpointer, memory reading means for reading numbers from said memory atsequential locations prescribed by said decoding pointer, clock meansfor generating encoding and decoding clock signals, said addressingmeans including means for incrementing said encoding pointer in responseto said encoding clock and for incrementing said decoding pointer inresponse to said decoding clock, and for shifting said encoding anddecoding pointers to a predetermined low address in said memory (e.g.,the zero address) after a predetermined higher address (e.g., thehighest address) is reached, means for varying the frequency of saiddecoding clock relative to said encoding clock, thereby to vary addressseparation between said encoding and decoding pointers and the amount ofdelay of said audio signal.
 2. The system of claim 1 furthercomprisingencoding means for encoding said audio signal to form saidsequence of numbers, said encoding means generating a new said number inresponse to said encoding clock, and decoding means for decoding saidnumbers read from said memory means to form a decoded audio signal, saiddecoding means decoding a new number in response to said decoding clock.3. The system of claim 2 wherein said encoding and decoding meanscomprise means for adaptive delta encoding and decoding, said numbersare individual bits, and said encoding and decoding pointers areincremented by a single bit at each encoding and decoding clock pulse,respectively.
 4. The system of claim 1 wherein said means for varyingcomprises means for prescribing the difference in frequency between saidencoding and decoding clocks.
 5. The system of claim 4 furthercomprising a processor and program storage means for storing softwarecontrolling said processor, said processor and software prescribing saiddifference in frequency.
 6. The system of claim 4 further comprisingmeans for prescribing a programmed sequence of frequency differencesover time to create a variation in delay useful for providing a flangeeffect.
 7. The system of claim 1 further comprisingmeans forindefinitely holding in said memory means a sequence of said numbersrepresenting an interval of said audio signal, means for repetitivelyreading all or a portion of said numbers from said memory means toprovide a repetitive playback of said stored interval of said audiosignal, means for varying the beginning and end points of said readportion thereby to vary the beginning and end points of saidrepetitively played back audio signal, said means comprising means forselecting two addresses between which said decoding pointer skips duringeach repetition of said stored interval.
 8. A memory addressing systemcomprisinga processor for prescribing the high-order portion of a memoryaddress, a counter for prescribing the low-order portion of said memoryaddress, processor clock means for operating said processor at aprocessor clock rate, counter clock means for operating said counter ata counter clock rate, said counter clock rate being at least four timessaid processor clock rate, means for providing an overflow indication tosaid processor when said counter has overflowed, means for incrementingsaid high-order address portion in response to said overflow indication.9. The system of claim 8 further comprisingan address register forstoring said high-order address portion, a buffer register for storingthe next value of said high-order address portion, means for loadingsaid address register with the contents of said buffer register uponassertion of said overflow indication, and means for loading said bufferregister with a new value of said high-order address portion in lessthan the time interval between successive overflow indications.
 10. Thesystem of claim 8 wherein said counter clock rate is at least eighttimes said processor clock rate.
 11. The system of claim 8 wherein saidsystem forms part of a system for variably delaying an audio signal,said system comprisingmemory means for storing a sequence of numberscomprising digital representions of consecutive portions of said audiosignal, said first-mentioned counter providing the low-order portion ofan encoding pointer for addressing said memory means, a second saidcounter providing the low-order portion of a decoding pointer foraddressing said memory means, memory writing means for writing saidnumbers at sequential memory locations prescribed by said encodingpointer, memory reading means for reading numbers from said memory atsequential locations prescribed by said decoding pointer, saidfirst-mentioned counter being operated at an encoding clock rate, saidsecond counter being operated at a decoding clock rate, said processorproviding the high-order portions of said encoding and decodingpointers, said encoding and decoding clock rates each being at leastfour times greater than said processor clock rate.